Moore's law, which is based on empirical observations, predicts that the speed of integrated circuits (IC's) doubles every eighteen months As a result, IC's with faster microprocessors and memory are often available for use in the latest electronic products every eighteen months. Although successive generations of IC's with greater functionality and features may be available every eighteen months, this does not mean that they can then be quickly incorporated into the latest electronic products In fact, one major hurdle in bringing electronic products to market is ensuring that the IC's, with their increased features and functionality, work as intended.
IC's are designed to operate in either a test mode or an operation mode, To facilitate the configuration of the IC in a test mode, test logic is embedded on the IC which exchanges data through test pins on the IC using a standard test interface such as Joint Testing Action Group (JTAG) or a real time data exchange (RTDX) type of interface developed by Texas instruments, Inc. This test logic is typically referred to as design-for-test (DFT) technology.
One such DFT technology is a scan design which creates one or more scan chains by serially tying together internal logic such as a set of registers and flip-flops in the IC. During the test mode of operation for the integrated circuit scan data is loaded into the internal logic of the IC through the test interface. After loading the test data, the IC is instructed to perform whatever operations would be caused by the scan data being loaded into the internal logic to create a scan signature. The scan signature is then read out from the test interface and compared with expected results to determine the operability of the IC. As the amount of internal logic has increased proportional to the increases predicted by Moore's Law, the size of scan chains and scan signatures has caused scan testing to become a lengthy and costly part of the IC development. As such, the development of scan compression DFT techniques has been used to shorten the amount of time testing takes and reduce the amount of data exchanged between testing equipment and an IC.
Uninitialized register files can cause a problem for DFT techniques that use scan compression because the output of the register file is not known. This unknown output value corrupts the signature that is calculated by the scan compression logic, thus invalidating the test.
Some testing equipment is very inefficient at masking and removing unknown values. Uninitialized register files can also cause a problem for this test equipment and can increase test time and in turn increase test costs.